1. What Is the Die-to-Die Interconnect Market?
The Die-to-Die Interconnect Market covers the electrical interface standards, silicon photonic links, and electrical chiplet interconnect technologies that enable high-bandwidth, low-latency communication between separately manufactured semiconductor dies assembled in multi-chiplet packages. This interconnect infrastructure is what the chiplet disaggregation of complex SoC designs requires, aiming for system-level bandwidth performance approaching that of a monolithic integrated circuit. Die-to-die interconnect standards including UCIe Universal Chiplet Interconnect Express, Open HBI, and CHIP Alliance specifications define the signal, power, and protocol layers. Chiplet manufacturers must conform to these standards for interoperable multi-source chiplet assembly. Physical interconnect implementations span several distance ranges. Short-reach electrical bump arrays using micro-bumps or hybrid copper-copper bonds serve chiplets under one millimetre apart. Multi-die organic substrate routing handles chiplets one to five millimetres apart using standard C4 bump technology. Silicon photonic chip-to-chip links address chiplets separated by millimetres to centimetres where electrical signal integrity degrades at the required data rates. Commercial deployments have proven the chiplet interconnect architecture in volume production. Server processors use multiple compute chiplets connected to a central IO die. Premium laptop processors connect two dies through high-bandwidth die-to-die interconnect, and multi-die AI GPUs demonstrate the approach in high-performance computing markets.
2. Die-to-Die Interconnect Market Size & Forecast
3. Emerging Technologies
- UCIe Universal Chiplet Interconnect Express standardisation has founding member support from Intel, AMD, Qualcomm, Samsung, TSMC, and ASML. It provides the open chiplet ecosystem infrastructure that enables multi-source chiplet procurement. This avoids the proprietary interface lock-in that vendor-specific die-to-die interconnects create. It potentially enables a chiplet marketplace analogous to PCB component procurement.
- Hybrid bonding die-to-die interconnect using copper-to-copper direct bonds at sub-micron pitch achieves bandwidth density exceeding 10 terabits per second per square millimetre. Interconnect power efficiency falls below 0.5 picojoules per bit. This approaches the performance characteristics of monolithic integration while maintaining the manufacturing and sourcing flexibility of chiplet disaggregation.
- Silicon photonic chip-to-chip interconnect using silicon waveguides and integrated laser sources at data rates above 800 Gbps per optical channel enables board-level and system-level communication. It works at data rates and distances that electrical die-to-die interconnects cannot achieve without signal integrity degradation. Intel and Ayar Labs are developing co-packaged optics for data centre switch and AI cluster interconnect.
- Chiplet ecosystem market development requires the concurrent availability of verified chiplet IP, advanced packaging services capable of multi-chiplet assembly, and EDA tooling for multi-die design. These jointly enable the chiplet marketplace that the UCIe standard envisions. The maturity of all three components determines the pace of adoption beyond the captive internal chiplet use that AMD and Intel already deploy.
Comparable technologies are influencing adjacent market segments in similar ways. Read more in our Fan Out Wafer Level Packaging Market.
4. Key Market Opportunity
Substantial growth potential in the Die-to-Die Interconnect market is the UCIe ecosystem, where chiplet design companies need IP, testing tools, and packaging partners that support the standard. IP providers, EDA tool vendors, and OSATs building UCIe capability are positioned at the centre of the emerging chiplet supply chain. A parallel growth driver is driven by co-packaged optics for hyperscaler AI accelerators, where optical die-to-die interconnect will be necessary for the next generation of scale-up AI cluster bandwidth. As chiplet architectures proliferate and AI bandwidth requirements continue to increase, the addressable opportunity is growing from proprietary interconnect within single-vendor chiplet processors toward a standardised multi-vendor chiplet ecosystem.
5. Top Companies in the Die-to-Die Interconnect Market
The following organisations hold leading positions in the Die-to-Die Interconnect Market. The full report provides revenue share, SWOT analysis, and competitive benchmarking for each player.
- TSMC
- Intel
- Samsung
- Synopsys
- Cadence Design Systems
- Alphawave Semi
6. Market Segmentation
The Die-to-Die Interconnect Market is analysed across 3 segmentation dimensions. Revenue data, growth rates, and competitive intensity by sub-segment are available in the full report.
| Segmentation | Sub-Segments |
|---|---|
| By Technology | UCIeAIBBoWOptical |
| By Application | AI AcceleratorCPU ChipletGPU ChipletNetwork Processor |
| By Geography | North AmericaEuropeAsia PacificLatin AmericaMiddle East and Africa |
7. Key Market Trends (2026–2034)
Three major forces are shaping the Die-to-Die Interconnect Market trajectory over the forecast period:
UCIe Standardisation Has Created the Open Chiplet Interconnect Ecosystem That Enables Multi-Vendor Chiplet Assembly Without Proprietary Interface Lock-In.The UCIe 1.0 specification adopted by founding members Intel, AMD, ARM, TSMC, Samsung, Qualcomm, Google, Meta, Microsoft, and Broadcom defines 2D and advanced packaging physical layer variants supporting 32 GT/s to 128 GT/s bandwidth per lane and protocol layer options supporting CXL, PCIe, and streaming fabrics that enable heterogeneous chiplet integration across vendor and foundry boundaries. Intel's Foveros Omni packaging with UCIe interface enables Intel's Ponte Vecchio GPU to combine compute tiles from TSMC N5 with IO and HBM interface tiles from Intel 16nm process in a single package, demonstrating the multi-foundry heterogeneous integration that UCIe standardisation targets. The UCIe die-to-die interconnect latency of sub-5 nanoseconds end-to-end at 16mm interconnect distance, compared with sub-500ns for HBM2e and 70-80ns LPDDR5 off-package memory access, positions UCIe as the enabling technology for disaggregated SoC architectures where chiplet integration can achieve near-monolithic performance with multi-vendor, multi-node process flexibility.
Hybrid Bonding Die-to-Die Interconnect at Sub-Micron Pitch Is Achieving 10 Tbps per Square Millimetre Bandwidth Density That Approaches Monolithic Integration Performance.Intel's EMIB using a small silicon bridge die embedded in the package substrate to provide dense escape routing between adjacent chiplets achieves 55-micron bump pitch between chiplet interfaces versus the 130-micron pitch of standard flip-chip solder bump interconnects, increasing die-to-die bandwidth by 5x without the silicon interposer area cost that TSMC's CoWoS-S approach requires. The EMIB embedded bridge approach places a small silicon die fragment at the chiplet interface boundary to provide the metal routing layers that package substrate materials cannot achieve at fine pitch, and the selective EMIB placement means only the interface regions between communicating chiplets require dense interconnect rather than the full silicon interposer area that CoWoS requires beneath all chiplets. Shin-Etsu Chemical and Ajinomoto Fine-Techno's advanced package substrate materials enabling EMIB bridge embedding alongside standard organic substrate layers represent the materials innovation that makes Intel's EMIB approach commercially viable at the qualification and reliability levels that data centre product customers require.
Silicon Photonic Chip-to-Chip Links Are Enabling the Board-Level Interconnect Bandwidth That Electrical Die-to-Die Interfaces Cannot Maintain at Multi-Hundred-Gigabit Data Rates.BoW (Bunch of Wires) from OIF providing 112 Gbps per differential pair at 250-micron bump pitch targets low-cost commodity interconnect applications where bandwidth is the primary metric rather than latency or energy efficiency, and the Open HBI (High Bandwidth Interconnect) specification from CEA-LIST and imec targeting compute memory stacking provides the die-to-die protocol for compute-near-memory architectures. The standardisation landscape competition reflects the diverse packaging technology options from organic substrate flip-chip at 130-micron pitch, fan-out wafer-level packaging at 40-micron pitch, silicon interposer at 25-micron pitch, and hybrid bonding at 1-10 micron pitch that each suit different bandwidth and package cost requirements. The consolidation toward UCIe as the dominant chiplet standard is progressing as the broader industry ecosystem adoption creates the tool, IP, and package substrate supply chain support that enables UCIe-based chiplet products at multiple companies, reinforcing the standard's position despite competing specifications from the Open Domain Specific Architecture and other initiatives.
For related market intelligence, see the Semiconductor Packaging Market.
8. Segmental Analysis
By technology, the UCIe and chip-to-chip interconnect segment dominated the Die-to-Die Interconnect Market in 2025, as TSMC CoWoS and EMIB from Intel anchored chiplet assembly for AMD EPYC and Intel Meteor Lake designs, generating the foundational commercial revenue in the category.
By application, the AI accelerator and chiplet integration segment is projected to register the highest growth rate through 2034, as the UCIe consortium standard enables multi-vendor chiplet sourcing that allows GPU and AI-accelerator designers to integrate compute, memory, and I/O dies from different foundries in a single package.
9. Regional Analysis
Regional demand patterns across the Die-to-Die Interconnect Market reflect differences in regulation, technological maturity, and capital investment.
Largest Market Share
North America dominated the Die-to-Die Interconnect Market in 2025, accounting for approximately 34% of global revenue, due to Intel and AMD as the most advanced chiplet architecture deployers and Synopsys and Cadence as UCIe IP and EDA tool providers. Moreover, the concentration of hyperscaler custom AI silicon programmes at US technology companies sustains the largest chiplet interconnect design activity. In addition, UCIe consortium leadership by US companies shapes the standard's direction. Regional leadership is attributed to this combination of design leadership and standards participation.
Highest CAGR Region
Asia Pacific is projected to register the highest CAGR in the Die-to-Die Interconnect Market through 2034, driven by TSMC's CoWoS and SoIC packaging capacity enabling the majority of advanced chiplet assemblies and the concentration of chiplet-based AI accelerator production at TSMC and Samsung. The region is also witnessing growing fabless chiplet design activity in Taiwan and South Korea. Moreover, Chinese foundries are developing domestic chiplet interconnect capabilities for domestic AI chip programmes. The combination of these demand drivers and packaging capacity concentration positions Asia Pacific for sustained growth outperformance through 2034.
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Frequently Asked Questions
The Die-to-Die Interconnect Market was valued at USD 1.85 Bn in 2025 and is projected to reach USD 26.65 Bn by 2034, growing at a CAGR of 34.5% over the 2026–2034 forecast period.
The Die-to-Die Interconnect Market is projected to grow at a CAGR of 34.5% from 2026 to 2034.
North America dominated the Die-to-Die Interconnect Market in 2025, accounting for approximately 34% of global revenue, due to Intel and AMD as the most advanced chiplet architecture deployers and Synopsys and Cadence as UCIe IP and EDA tool providers.
The leading companies in the Die-to-Die Interconnect Market include TSMC, Intel, Samsung, Synopsys, Cadence Design Systems, Alphawave Semi.
Ucie standardisation has created the open chiplet interconnect ecosystem that enables multi-vendor chiplet assembly without proprietary interface lock-in.
By technology, the UCIe and chip-to-chip interconnect segment dominated the Die-to-Die Interconnect Market in 2025, as TSMC CoWoS and EMIB from Intel anchored chiplet assembly for AMD EPYC and Intel Meteor Lake designs, generating the foundational commercial revenue in the category.
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